One embodiment of the invention relates to a novel hard mask layer stack. In addition, one embodiment of the invention relates to a method of patterning a layer using this hard mask layer stack. Furthermore, one embodiment of the invention relates to a memory device, a method of forming a memory device and to masks used by this method.
Semiconductor devices include arrays of conductive lines in several layers of the device. The conductive lines of such arrays usually are arranged in parallel and are electrically insulated from one another laterally by a dielectric material. The lateral distance between two conductive lines and the width of a conductive line sum to the pitch of the array of lines. The pitch is the dimension of the periodicity of a periodic pattern arrangement. The lines succeed one another in a completely periodic fashion, in order to reduce the necessary device area as much as possible.
By way of example, semiconductor memory devices include arrays of conductive lines which connect specific parts of memory cells arranged in rows and columns and which thus address the memory cells. Nevertheless, it is not necessary to address each memory cell separately. Usually, two sets of conductive lines are formed where the first set runs along a first direction and is called word lines and where the second set runs along a second direction intersecting the first direction and is called bit lines. Usually word or bit lines are formed by patterning a conductive layer stack so as to form single lines which are arranged in parallel.
Nevertheless, a semiconductor device may include arrays of conductive lines in other layers than the word or bit line layer.
FIG. 1A illustrates a plan view of an exemplary memory device comprising an array 100 of memory cells. To be more specific, the memory cell array 100 includes word lines 2 extending in a first direction as well as bit lines extending in a second direction. Memory cells 45 are disposed between adjacent bit lines at each point of intersection of a substrate portion with a corresponding word line 2. At a point of intersection of the word lines and bit lines, the bit lines and the word lines are insulated from each other by a thick silicon dioxide layer (not shown). In order to minimize the area for the memory cell array 100, the pitch of the array of the word lines is reduced as much as possible. Nevertheless, for contacting the single word lines landing pads 111 having a minimum area are needed. Usually, these landing pads 111 are disposed in a contact or fanout region 110 adjacent to the memory cell array 100. In order to achieve a contact having an appropriate contact resistance, the area of each of the landing pads 111 must have a minimum value. Furthermore, a minimum value of the landing pads is needed to securely make a contact to upper wiring layers without having challenging overlay specifications.
As is illustrated in FIG. 1A, the word lines 2 have a minimum width wmin and a minimum distance dmin from each other. In order to increase the package density of such a memory cell array, the width and the distance of the word lines could be reduced. However, when shrinking the width of the word lines 2, a minimum contact area in the contact region 110 should be maintained. Differently stated, the difference in size between the width of the word lines 2 and the lateral dimensions of the landing pads 111 becomes greater.
Different problems arise from the shrinking in the width and pitch of the word lines. For example, landing pads 111 which have a relatively large area with respect to the width of the word lines have to be arranged at the end of each word line without contacting or affecting each other. One solution to this is the arrangement of landing pads at both sides of the array, as illustrated in FIG. 1B. Having landing pads of only every second word line at one side of the array, the landing pads can have a large area without contacting or affecting neighbouring landing pads. However, the arrangement of landing pads at both sides of the array results in a complex wiring scheme in upper layers affecting the performance of the memory device. For example, lines have to be generated in another layer that connect every second pad at the other side of the array.
A further problem that arises from the shrinking the pitch of the word lines relates to the patterning of these small structures. If the word line array is patterned by using a photolithography technique that is usually employed, the lateral dimensions of the word lines as well as the distance between neighbouring word lines is limited by the minimal structural feature size which is obtainable by the technology used. However, a lithographic step for simultaneously imaging different ground rules (large area of landing pads and small conductive lines) is very difficult to implement, since the lithographic step and the used mask have to be optimized for imaging the smallest structure. Therefore, further shrinking of word line width and pitch (word line width smaller than 70 nm), and thus further shrinking of memory devices, is difficult using a single exposure lithography.
Although these problems are described herein for word line arrays of memory devices by way of example, they are likely to arise for other devices or for other wiring layers as well when these devices or wiring layers reach comparable dimensions.